Server computers and even some personal computers (PCs) are commercially available with multiprocessing capability. A typical multiprocessor architecture may include a hub referred to as the “central agent” for handling memory transactions, input/output (I/O), etc., in addition to one or more processing units which may execute in parallel to increase overall throughput and performance of the computer system.
In a multiprocessor architecture, the central agent and processing units are typically coupled to one another for data transfer over a system bus, also referred to as a front side bus (FSB). Accordingly, the computer system's throughput and performance depends at least to some extent on the rate at which data is transferred over the system bus. During an exemplary operation, data and strobes are alternately driven onto the system bus in a quadrature phase relationship (i.e., at fixed 90 degree offsets) with respect to the bus clock. Idle bus clock cycles are imposed between each data transfer operation to allow time for the data driven to propagate to all agents attached to the bus. After one or more idle cycles on the bus, the system bus is available for use by another agent. The throughput and performance of the computer system is decreased because the frequency at which the system bus is operated is reduced to allow time for proper signaling.